1. Field of the Invention
The present invention relates to a phase locked loop circuit, and more particularly to a phase locked loop circuit adopted for controlling a so-called on-screen display (OSD) operation which is performed by a video cassette recorder (VCR) or the like for displaying characters on a monitor screen connected thereto, and also relates to a method of controlling jittery movements of the characters formed by the OSD operation for use in the phase locked loop circuit.
2. Description of the Related Art
FIG. 5 is a schematic diagram showing a conventional phase locked loop circuit adopted for controlling the OSD operation. In the same figure, reference numeral 51 denotes a phase comparator, numeral 52 denotes a charge pump, numeral 53 denotes a low-pass filter (abbreviated to xe2x80x9cLPFxe2x80x9d hereinafter), 54 denotes a voltage-controlled oscillator (abbreviated to xe2x80x9cVCOxe2x80x9d hereinafter), and numeral 55 denotes a frequency divider. The output of the frequency divider 55 is fed back to the phase comparator 51.
The operation of the phase locked loop circuit (hereinafter may be referred to just as a xe2x80x9cPLL circuitxe2x80x9d) configurated as above is now explained below.
The PLL circuit 51 detects the difference in phase between a signal input from outside the PLL circuit (hereinafter referred to as an xe2x80x9cexternally input signalxe2x80x9d or just as an xe2x80x9cexternal signalxe2x80x9d) and an output signal fed back from the frequency divider 55. The phase difference signal obtained by this detection executed in the phase comparator 51 is fed to the LPF 53 by way of the charge pump 52. The LPF 53 receives the phase difference signal, and regulates the level of the thus input phase difference signal. The signal regulated by the LPF 53 is then fed to the VCO 54 as the control signal thereof. The signal output from the VCO 54 is then fed to the frequency divider 55, and divided therein. The signal which is divided and outputted from the frequency divider 55 is then fed back to the phase comparator 51, so as to detect the phase difference between the output signal fed from the frequency divider 55 and the externally input signal.
Since the conventional PLL circuit is configurated as such, the phase locking operation is performed solely at a predetermined constant responsive rate which is determined in accordance with the time constant of the LPF 53, irrespective of the level of the external signal. Accordingly, in a case in which the PLL circuit of the above configuration is adopted for controlling the OSD operation, there has been such a drawback that it cannot efficiently cope with the jittery movements of the characters formed by the OSD operation (abbreviated hereinafter to the xe2x80x9cOSD charactersxe2x80x9d).
The present invention has been proposed to solve the problems aforementioned, and it is an object of the present invention to provide a PLL circuit equipped with a function capable of efficiently controlling the jittery movements (or simply xe2x80x9cjitterxe2x80x9d) of the OSD characters at a high responsive rate by varying and setting the time constant of the LPF to an optimum value under control of the CPU.
In order to achieve the above object, the PLL circuit according to the first aspect of the present invention is constructed such that it comprises: a phase comparing means, a charge pump connected to the phase comparing means, a variable low-pass filter connected to the charge pump, the time constant of which is variable, a voltage-controlled oscillation means connected to the low-pass filter, a frequency dividing means connected to the voltage-controlled oscillation means, and a control means for generating and outputting a control signal for varying the time constant of the low-pass filter, wherein the phase comparing means receives an external signal used for controlling an on-screen display function and an output signal from the frequency dividing means, and detects the phase difference between the phase of the external signal and that of the output signal from the frequency dividing means, and the control means generates a control signal for changing the time constant to a predetermined value in accordance with the state of the external signal used for controlling the on-screen display function, and outputting the control signal to the variable low-pass filter to change the time constant of the variable low-pass filter, thereby to control jittery movements of the characters displayed by the on-screen display function.
According to the second aspect of the present invention, the low-pass filter in the phase locked loop circuit further comprises: a first resistor, a third resistor connectable in parallel with the first resistor, a first capacitance connected to a portion between the first resistor and the ground potential, a second resistor and a second capacitance, which are mutually connected in series, connected to a portion between the first resistor and the grand potential, and a first switching means that connects the third resistor to the first resistor in parallel in accordance with the control signal from the control means, and also connects the third resistor to the first capacitance, and to the series-connected second resistor and second capacitor, thereby to set the time constant of the variable low-pass filter to a predetermined value.
According to the third aspect of the present invention, the low-pass filter in the phase locked loop circuit further comprises: a fourth resistor, a third capacitance connected to a portion between the fourth resistor and the ground potential, a fourth capacitance and a fifth resistor, which are mutually connected in series, connectable to a portion between the fourth capacitance and the ground potential, a fifth capacitance and a;sixth resistor, which are mutually connected in series, connectable to a portion between the fourth capacitance and the ground potential, and a second switching means that connects the fourth resistor either to the series-connected fifth resistor and the fourth capacitance, or to the series-connected sixth resistor and the fifth capacitance, thereby to set the time constant of the variable low-pass filter to a predetermined value.
According to the fourth aspect of the present invention, the low-pass filter in the phase locked loop circuit further comprises:
a seventh resistor, an eighth resistor connectable in parallel with the seventh resister, a sixth capacitance connected to a portion between the seventh resistor and the ground potential, a seventh capacitance connected to a portion between the seventh resistor and the ground potential, and a third switching means that connects the eighth resister to the seventh resistor in parallel in accordance with the control signal from the control means, and also connects the eighth resistor either to the sixth capacitance or to the seventh capacitance, thereby to set the time constant of the variable low-pass filter to a predetermined value.
According to the fifth aspect of the present invention, a method of controlling jitter of characters formed by an on-screen display function by use of a phase locked loop circuit which comprises at least a phase comparator, a low-pass filter having a switching means for selecting one of at least two time constants, a voltage-controlled oscillator, and a frequency divider, includes the steps of: inputting an external signal used for controlling a non-screen display function and an output signal from the frequency divider to the phase comparator, so as to detect the phase difference between the input signals, feeding the signal indicating the phase difference to the variable low-pass filter, generating a control signal in the control means and outputting the control signal to the variable low-pass filter, and activating the switching means for selecting one of the time constants in accordance with the state of the external signal.
Since the phase locked loop circuit according to the present invention is configured such that the CPU changes the time constant of the variable LPF filter to an optimum value in accordance with the state of the external signal fed from outside, for example by way of the selection switch activated in accordance with a control signal fed from the CPU, the responsive rate of the PLL circuit is raised, so that it can cope with the jitter phenomenon generated due to noise or a fluctuation of the supply voltage of the PLL circuit itself.
On the other hand, in a case in which an external signal itself fed from outside the PLL circuit includes a considerable amount of noise or signal loss in itself, the CPU switches the time constant of the variable low-pass filter in accordance with the state of the external signal, and thereby sets the responsive rate of the PLL circuit to an optimum level, so that a fluctuation of the PLL circuit itself is suppressed, and the jitter of the OSD characters can thereby be eliminated.